diff --git a/pkgs/applications/science/electronics/vhd2vl/default.nix b/pkgs/applications/science/electronics/vhd2vl/default.nix
index f0dd990a35bc..089ebb9bb198 100644
--- a/pkgs/applications/science/electronics/vhd2vl/default.nix
+++ b/pkgs/applications/science/electronics/vhd2vl/default.nix
@@ -1,6 +1,5 @@
 { lib, stdenv
 , fetchFromGitHub
-, fetchpatch
 , bison
 , flex
 , verilog
@@ -19,12 +18,8 @@ stdenv.mkDerivation rec {
   };
 
   patches = lib.optionals (!stdenv.isAarch64) [
-    # fix build with verilog 11.0 - https://github.com/ldoolitt/vhd2vl/pull/15
-    # for some strange reason, this is not needed for aarch64
-    (fetchpatch {
-      url = "https://github.com/ldoolitt/vhd2vl/commit/ce9b8343ffd004dfe8779a309f4b5a594dbec45e.patch";
-      sha256 = "1qaqhm2mk66spb2dir9n91b385rarglc067js1g6pcg8mg5v3hhf";
-    })
+    # fix build with verilog 11.0
+    ./test.patch
   ];
 
   nativeBuildInputs = [
@@ -37,6 +32,13 @@ stdenv.mkDerivation rec {
     verilog
   ];
 
+  # the "translate" target both (a) builds the software and (b) runs
+  # the tests (without validating the results)
+  buildTargets = [ "translate" ];
+
+  # the "diff" target examines the test results
+  checkTarget = "diff";
+
   installPhase = ''
     runHook preInstall
     install -D -m755 src/vhd2vl $out/bin/vdh2vl
diff --git a/pkgs/applications/science/electronics/vhd2vl/test.patch b/pkgs/applications/science/electronics/vhd2vl/test.patch
new file mode 100644
index 000000000000..85b91964e392
--- /dev/null
+++ b/pkgs/applications/science/electronics/vhd2vl/test.patch
@@ -0,0 +1,35 @@
+--- a/translated_examples/fifo.v  1970-01-01 00:00:01.000000000 +0000
++++ a/temp/verilog/fifo.v 2022-05-11 03:44:43.173604945 +0000
+@@ -107,7 +107,7 @@
+   //--- Read address counter --------------
+   //---------------------------------------
+   assign add_RD_CE = (iempty == 1'b1) ? 1'b0 : (RD == 1'b0) ? 1'b0 : 1'b1;
+-  assign n_add_RD = (add_RD) + 4'h1;
++  assign n_add_RD = add_RD + 4'h1;
+   always @(posedge clk_RD, posedge rst) begin
+     if((rst == 1'b1)) begin
+       add_RD <= {5{1'b0}};
+diff -u '--exclude=Makefile' '--exclude-from=examples/exclude' translated_examples/test.v temp/verilog/test.v
+--- a/translated_examples/test.v  1970-01-01 00:00:01.000000000 +0000
++++ a/temp/verilog/test.v 2022-05-11 03:44:43.189604945 +0000
+@@ -125,7 +125,7 @@
+     endcase
+   end
+
+-  assign code1[1:0] = a[6:5] ^ ({a[4],b[6]});
++  assign code1[1:0] = a[6:5] ^ {a[4],b[6]};
+   // Asynch process
+   always @(we, addr, config1, bip) begin
+     if(we == 1'b1) begin
+diff -u '--exclude=Makefile' '--exclude-from=examples/exclude' translated_examples/withselect.v temp/verilog/withselect.v
+--- a/translated_examples/withselect.v    1970-01-01 00:00:01.000000000 +0000
++++ a/temp/verilog/withselect.v   2022-05-11 03:44:43.193604945 +0000
+@@ -33,7 +33,7 @@
+     endcase
+   end
+
+-  assign code1[1:0] = a[6:5] ^ ({a[4],b[6]});
++  assign code1[1:0] = a[6:5] ^ {a[4],b[6]};
+   assign foo = {(((1 + 1))-((0))+1){1'b0}};
+   assign egg = {78{1'b0}};
+   assign baz = {(((bus_width * 4))-((bus_width * 3 - 1))+1){1'b1}};