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@ -37,7 +37,7 @@ in stdenv.mkDerivation rec {
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src/Verilog/copy_module.pl \
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src/comp/update-build-version.sh \
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src/comp/update-build-system.sh \
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src/comp/wrapper.sh
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src/comp/wrapper.sh
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substituteInPlace src/comp/Makefile \
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--replace 'BINDDIR' 'BINDIR' \
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