50 lines
1.6 KiB
Nix
50 lines
1.6 KiB
Nix
{ stdenv, fetchFromGitHub, fetchFromBitbucket, pkgconfig, tcl, readline, libffi, python3, bison, flex }:
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stdenv.mkDerivation rec {
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name = "yosys-${version}";
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version = "2017.09.01";
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srcs = [
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(fetchFromGitHub {
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owner = "cliffordwolf";
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repo = "yosys";
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rev = "18609f3df82a3403c41d552908183f7e49ff5678";
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sha256 = "0qdjxqg3l098g8pda5a4cif4bd78rx7vilv3z62r56ppj55mgw96";
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name = "yosys";
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})
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(fetchFromBitbucket {
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owner = "alanmi";
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repo = "abc";
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rev = "ff5be0604997";
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sha256 = "08gdvxm44dvhgjw6lf2jx0xyk6h4ai37h6b88dysvaa69sx7rh8n";
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name = "yosys-abc";
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})
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];
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sourceRoot = "yosys";
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buildInputs = [ pkgconfig tcl readline libffi python3 bison flex ];
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preBuild = ''
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chmod -R u+w ../yosys-abc
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ln -s ../yosys-abc abc
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make config-gcc
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echo 'ABCREV := default' >> Makefile.conf
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makeFlags="PREFIX=$out $makeFlags"
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'';
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meta = {
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description = "Framework for RTL synthesis tools";
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longDescription = ''
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Yosys is a framework for RTL synthesis tools. It currently has
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extensive Verilog-2005 support and provides a basic set of
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synthesis algorithms for various application domains.
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Yosys can be adapted to perform any synthesis job by combining
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the existing passes (algorithms) using synthesis scripts and
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adding additional passes as needed by extending the yosys C++
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code base.
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'';
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homepage = http://www.clifford.at/yosys/;
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license = stdenv.lib.licenses.isc;
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maintainers = [ stdenv.lib.maintainers.shell ];
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platforms = stdenv.lib.platforms.linux;
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};
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}
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